The present invention relates generally to a process for forming a semiconductor device, and more particularly, to a process for forming an interconnect structure in a semiconductor and its method of formation.
Semiconductor devices are continuing to being scaled to smaller dimensions. As the size of interconnects making up the various levels of the semiconductor devices continue to decrease, so to does the spacing between them. The combination of smaller linewidths and spacing introduces new problems with respect to the interconnect""s resistance and capacitance. The smaller linewidth dimensions increases the resistance (R) of the conductive lines. The reduction in spacing between conductive lines increases the capacitance (C) between them. The associated resistance-capacitance (RC) coupling introduces problems with respect to propagation delay, crosstalk noise, and power dissipation of the device circuitry.
Copper interconnect technology and low dielectric constant (low-k) materials are two areas currently being developed by semiconductor device manufacturers in an effort to overcome the problems associated with increasing resistance and capacitance. The dielectric constant of a material separating two conducting films directly impacts the interconnect capacitance of a semiconductor device. To address these problems, new materials having lower dielectric constants are being investigated to replace dielectric films commonly used in semiconductor device fabrication. Air has a dielectric constant, or k value equal to one, and is considered to be the perfect insulator. Commonly used silicon dioxide (SiO2), by comparison, has a dielectric constant of approximately 4.2. For the purposes of this specification, a low-k material for use as a semiconductor insulator is any material having a dielectric constant less than approximately 3.5.
In one particular interconnect scheme, a dual inlaid structure is formed. After forming a first interconnect level, an interlevel dielectric (ILD) layer having a dual inlaid opening is formed. One technique in the prior art uses three relatively high dielectric constant hardmask films with low-k dielectric films layered between them. The dual inlaid structure is formed by opening a via and a trench in the dielectric films using a xe2x80x9cvia first, trench lastxe2x80x9d or xe2x80x9ctrench first, via lastxe2x80x9d processing sequence. Following these steps, an interconnect structure is formed within the trench and the via opening.
One problem with the prior art includes its use of chemically vapor deposited silicon nitride materials, including plasma enhanced silicon nitride or silicon oxynitride compounds to form a hardmask film that separates the low-k dielectric films. These materials have a relatively high dielectric constant (i.e., greater than five) that increases the total dielectric constant of the ILD layer and raises the line-to-line capacitance within the device. Additionally, the use of multiple hardmask films further complicates the manufacturing process by requiring additional film depositions and etch processes to be incorporated into the process flow in order to manufacture the semiconductor device.